The iAPX family of single chip microprocessors is widely used in personal computers. Microprocessors termed the 8086, 80286, 80386 and 80486 are members of the iAPX family of microprocessors. Microprocessors in the iAPX 86 family are commercially available from a number of vendors including Nippon Electric Corporation (generally known as NEC), Advanced Micro Devices Corporation (generally known as AMD), Intel Corporations, and Chips and Technologies Incorporated.
Microprocessors in the iAPX family require an external clock signal and microprocessors are generally sold with a specification concerning the speed at which the particular microprocessor can operate. Microprocessors which can operate at 16, 20, 25, 33, and 40 MHz are widely available.
The iAPX family of single chip microprocessors are designed to operate with a synchronous input-output bus. That is, the clock cycle for the memory and the memory bus are synchronized with the operation of the CPU. Thus, if the CPU is operating at 33 MHz, the memory and the memory bus also operate at 33 MHz.
The present invention provides a system where the CPU operates at a multiple of the speed of the memory and memory bus. The present invention is particularly useful with the 486 family of microcomputers because the 486 microcomputers include a memory cache on the microprocessor chip.
Two broad categories of memory caches are known. The first type of cache is termed a write-thru cache. With a write-thru cache, each time data is written from the CPU to memory the cache memory is updated and the data is written over the memory bus to the main memory. The second type of cache is termed a write-back cache. With a write-back cache, when the CPU modifies data which is stored in the cache, the data is written back into the cache, but this data is not written to the main memory until the data in the cache is displaced by more recently accessed data.
The present invention takes particular advantage of the characteristics of a write-back cache to achieve improved performance. The combination of doubling the CPU clock and providing a write-back cache is truly synergistic. If the memory bus of a system is in use fifty percent of the time in a system where the memory system and CPU are operating at the same clock speed, it is not possible to double the clock speed of the CPU and assume that the memory bus will be in use one hundred percent of the time. Among the reasons for this is that the bus may be in the middle of a cycle rather than at the beginning of a cycle when the CPU calls for an input-output cycle. If the bus is in the middle of a bus cycle when the CPU calls for an I-O cycle the CPU must wait until the beginning of the next bus cycle. Such waiting reduces the benefit one might expect from doubling the clock speed.
In a 486 microprocessor, which has a write-thru cache, the bus utilization is about fifty percent. If one makes a simple calculation of bus utilization in a system where (a) the CPU clock rate is twice the bus clock rate, (b) the system includes a write-thru cache, and (c) the CPU is operating at 100%, one would project a bus utilization or demand of about 110 to 120 percent. Naturally, in most practical applications, bus demand is not steady, but the point is that in the situation described above, the projected demand would exceed one hundred percent and the system would be bus limited. Stated differently, since at most, the bus can be used 100 percent of the time, in such a system the CPU will of necessity have to wait for the bus and therefore the CPU will operate less than 100 percent of the time.
In a 486 system where the CPU and the bus are operating at the same speed, if the write-thru cache is replaced by a write-back cache, bus utilization will be about fourteen percent. If the present invention is used to double the CPU clock speed, the bus utilization will go to approximately thirty five percent. Thus by both doubling the CPU speed and using a write-back cachet, the present invention achieves its true potential relative to increased CPU speed.